At the first glance, it’s a very easy task. However it has a number of less obvious pitfalls when you’re working with microcontrollers via some kind of gdb stub or openocd and the memory you’re actually uploading your .bin file is the flash memory of an MCU (e.g. stm32). I decided to gather the common pitfalls in a single blog post.
A usual rant goes towards ST guys for their mindless design*. I don’t really know anyone, who does some heavy app development with no serial terminal for debugging (Or may be I don’t know many of them?). You know, gdb is good, but a good old ‘dmesg’-like stuff is usually even more helpful.
Anyway, while other people are trying to discover traces of sanity of the ST people by reversing STLinkv2 and discovering only huge holes in security so far, I decided to go a different way that works just fine with STLinkV1 and STLinkV2.
My first idea was to stuff the VCP example into the stlink’s uC (which is an STM32F103C8T6) and throw a little wires, but in the end – I didn’t want to ditch STLink completely (It helped me out a few times). Ideas? Sure!
First step. What does STLink do? Right, apart from that breakpoint/step voodoo it writes and reads memory. Sounds good? Good! Enough to do pretty much anything.
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Okay, lately I’ve been quite busy routing another killerboard with a friend of mine. With STM32 and Xilinx FPGA on the memory bus. These babies are intended for use in some robots, will post some details later. If I get a chance.
Anyway, the boards arrived, I quickly ported my Xilinx-sscu driver to bare metal and… pooh, it didn’t work.
It took me quite a while poking with an osclilloscope: I adjusted delays, added caps to CLK & DIN lines to remove spikes – same shit. Then I accidentally disabled the oscillator for the FPGA… And guess what – it worked. I enabled the oscillator after config was done – the FPGA started blinking happily. WTF?
Looks like I’ll have to add another wire for toggling oscillator from uC.
No sources or kicad circuitry YET. Just a pic of the board for now, it’s in REALLY early testing stage.
