Tag Archives: asic

The painfull verilog preprocessor pitfall

Just a little note about how includes and `defines work in verilog which is VERY different from how they behave in most programming languages. This may not really hurt in a small project, but can become a real PITA in a big project with a dozen of third-party blocks.

TL;DR: Macro defines are have a global scope in verilog and propagate from file to file during one tool invocation.

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